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Espressif Systems /ESP32-C3 /SPI0 /MISC

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Interpret as MISC

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (TRANS_END)TRANS_END 0 (TRANS_END_INT_ENA)TRANS_END_INT_ENA 0 (CSPI_ST_TRANS_END)CSPI_ST_TRANS_END 0 (CSPI_ST_TRANS_END_INT_ENA)CSPI_ST_TRANS_END_INT_ENA 0 (CK_IDLE_EDGE)CK_IDLE_EDGE 0 (CS_KEEP_ACTIVE)CS_KEEP_ACTIVE

Description

SPI0 misc register

Fields

TRANS_END

The bit is used to indicate the spi0_mst_st controlled transmitting is done.
TRANS_END_INT_ENA

The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done.
CSPI_ST_TRANS_END

The bit is used to indicate the spi0_slv_st controlled transmitting is done.
CSPI_ST_TRANS_END_INT_ENA

The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.
CK_IDLE_EDGE

1: spi clk line is high when idle 0: spi clk line is low when idle
CS_KEEP_ACTIVE

spi cs line keep low when the bit is set.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data